1. Field of the Invention
The present invention relates to a data processing circuit, particularly to a data processing circuit including a register capable of rewriting only data of a portion of a designated size for writing, and an arithmetic and logic unit.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration example of a conventional data processing circuit composed of an arithmetic and logic unit (ALU) 4 dealing with data of four bytes (one word) and a register file 1.
The ALU 4 performs operation of data respectively inputted from an S1 bus 6 and an S2 bus 7, and outputs the operation result to a D bus 8 in four bytes.
The register file 1 is composed of 16 registers 11 each of which is 32 bits (four bytes), and one of the register 11 is selected and the operation result by the ALU 4 is inputted thereto from the D bus 8 and stored.
And data is outputted from the respective registers 11 to the S1 bus 6 and S2 bus 7.
In this data processing circuit, it is possible to deal with three kinds of sizes of byte, half word, and word, and the respective data length are shown in the following;
byte: one byte (eight bit)
half word: two byte (16 bits )
word: four byte (32 bits)
In each register 11, only data corresponding to a designated size is written and data other than that is to kept an original value, that is, a value before a new data is written
FIG. 2 shows bit positions which data of the respective sizes occupy in 32 bits of each register 11.
A byte size data is effective in lower one byte (24:31) of the register 11, a half word size data is effective in lower two bytes (16:31) of the register 11, and a word size data is effective in all of the four bytes (0:31) of the register 11.
In order to control writing by the three kinds of size to each register 11, each conventional register 11 is provided with a select and input circuit 13. One register 11 is provided with one select and input circuit 13, and the two configures one register unit 10.
The select and input circuit 13 is controlled by a control signal to be described later, selects whether or not write data inputted from the D bus 8 and writes data only to a designated portion according to the writing sizes of the register 11.
FIG. 3 is a concrete configuration of each register unit 10.
Three control signal are necessary to input three kinds of data.
That is, the first select and input circuit 131 for inputting lower one byte (24:31) to the register 11 is controlled by a control signal C1 to select whether or not write data from the D (24:31) 83 which is a portion of the D bus 8. The second select and input circuit 132 for inputting one byte (16:23) being upper than the D (24:31) 83 to the register 11 is controlled by a control signal C2 to select whether or not write data from the D (16:23) 82 which is a portion of the D bus 8. The third select and input circuit 133 for inputting the upper two bytes (0:15) to the register 11 is controlled by a control signal C3 to select whether or not write data from the D (0:15) 81 which is a portion of the D bus 8.
When word is designed as the writing size, all of the control signals C1, C2 and C3 become "1" and D (0:31), that is, all the data of the D bus 8 is written into the register 11.
When half word is designated as the writing size, the control signal C1 and C2 become "1" and D (16:31), that is, data of the D (16:23) 82 and the D (24:31) 83 is written into the lower two bytes of the register 11.
When byte is designated as the writing size, only the control signal C1 becomes "1" and the at a of the D (24:31) 83 is written into the lower one byte of the register 11.
By the way, since one select and input circuit 13 is necessary for each register unit 10 together with one register 11, as the number of the registers 11 increases, the number of the select and input circuits 13 increase, thereby the occupying area on a chip, increases and since the number of the control signals increase, the wiring area therefor also increases.
And in a processor having a super scalar function, the register has a plurality of input ports. In this case, since the input control signal necessary for one register is "3.times. the number of the input ports", when the number of the registers increase, the occupying area on the chip further increases.
In such a prior art as aforementioned, since one select and input circuit is provided for each one register, there has been a problem that an occupying area of the register file on a chip is increased. It becomes obvious particularly when there are many registers or a register has a plurality of input ports.